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| DATASHEET LOW EMI CLOCK GENERATOR Description The IDT5V50017 generates a low EMI output clock from a clock input. The part is designed to dither the LCD interface clock for PDAs, printers, DTVs, scanners, modems, copiers, and others. Using IDT's proprietary mix of analog and digital Phase-Locked Loop (PLL) technology, the device spreads the frequency spectrum of the output, reducing the frequency amplitude peaks by several dB. IDT offers many other clocks for computers and computer peripherals. Consult IDT when you need to remove crystals and oscillators from your board. IDT5V50017 Features * * * * Packaged in 8-pin SOIC Provides a spread spectrum output clock 15 - 60 MHz operation Accepts a clock input (provides same frequency dithered output) * Down spread modulation * Peak reduction by 8 dB to 16 dB typical on 3rd through 19th odd harmonics * Low EMI feature can be disabled * Operating voltage of 3.3 V * Advanced, low-power CMOS process Block Diagram VDD S1:0 2 PLL Clock Synthesis and Spread Spectrum Circuitry SSCLK ICLK GND IDTTM LOW EMI CLOCK GENERATOR 1 IDT5V50017 REV D 040709 IDT5V50017 LOW EMI CLOCK GENERATOR SSCG Pin Assignment ICLK VDD GND SSCLK 1 2 3 4 8 7 6 5 VDD S0 S1 GND Spread Direction and Percentage Select Table S1 Pin 6 S0 Pin 7 Spread Direction Spread Percentage 0 0 1 1 0 1 0 1 OFF Down Down Down -1.0% -2.0% -3.0% 8 pin (150 mil) SOIC 0 = connect to GND 1 = connect directly to VDD Pin Descriptions Pin Number Pin Name Pin Type Pin Description 1 2 3 4 5 6 7 8 ICLK VDD GND SSCLK GND S1 S0 VDD Input Power Power Output Power Input Input Power 15-60 MHz clock input. Connect to +3.3 V. Connect to ground. Clock output with spread spectrum. Connect to ground. Function select 1 input. Selects spread amount and direction per table above. Internal pull-down. Function select 0 input. Selects spread amount and direction per table above. Internal pull-down. Connect to +3.3 V. IDTTM LOW EMI CLOCK GENERATOR 2 IDT5V50017 REV D 040709 IDT5V50017 LOW EMI CLOCK GENERATOR SSCG External Components The IDT5V50017 requires a minimum number of external components for proper operation. Spread Spectrum Profile The IDT5V50017 low EMI clock generator uses an optimized frequency slew rate algorithm to facilitate down stream tracking of zero delay buffers and other PLL devices. The frequency modulation amplitude is constant with variations of the input frequency. Decoupling Capacitor A decoupling capacitor of 0.01F must be connected between VDD and GND on pins 2 and 3, as close to these pins as possible. For optimum device performance, the decoupling capacitor should be mounted on the component side of the PCB. Avoid the use of vias in the decoupling circuit. Modulation Rate Series Termination Resistor When the PCB trace between the clock output and the load is over 1 inch, series termination should be used. To series terminate a 50 trace (a commonly used trace impedance) place a 33 resistor in series with the clock line, as close to the clock output pin as possible. The nominal impedance of the clock output is 20 . Frequency Time PCB Layout Recommendations For optimum device performance and lowest output phase noise, the following guidelines should be observed. 1) The 0.01F decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible. No vias should be used between the decoupling capacitor and VDD pin. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. 2) To minimize EMI, the 33 series termination resistor (if needed) should be placed close to the clock output. 3) An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers. Other signal traces should be routed away from the IDT5V50017. This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. IDTTM LOW EMI CLOCK GENERATOR 3 IDT5V50017 REV D 040709 IDT5V50017 LOW EMI CLOCK GENERATOR SSCG Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the IDT5V50017. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Item Supply Voltage, VDD All Inputs and Outputs Ambient Operating Temperature Storage Temperature Junction Temperature Soldering Temperature 7V Rating -0.5 V to VDD+0.5 V 0 to +70 C -65 to +150 C 125 C 260 C Recommended Operation Conditions Parameter Ambient Operating Temperature Power Supply Voltage (measured in respect to GND) Min. 0 +2.97 Typ. 3.3 Max. +70 3.63 Units C V IDTTM LOW EMI CLOCK GENERATOR 4 IDT5V50017 REV D 040709 IDT5V50017 LOW EMI CLOCK GENERATOR SSCG DC Electrical Characteristics Unless stated otherwise, VDD = 3.3 V, Ambient Temperature 0 to +70 C Parameter Operating Voltage Supply Current Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Input Capacitance Pull-down Resistance Note 1: CL = 15 pF. Symbol VDD IDD VIH VIL VOH VOL CIN1 RPD Conditions ICLK=50 MHz, Note 1 S1: S0 S1: S0 IOH = -6 mA IOH =- 20 mA IOL = 6 mA IOL = 20 mA All inputs S1, S0 Min. 2.97 2.0 Typ. 3.3 17 Max. 3.63 20 0.8 Units V mA V V V V 2.4 2.0 0.4 1.2 3 4 240 5 V V pF k AC Electrical Characteristics Unless stated otherwise, VDD = 3.3 V, Ambient Temperature 0 to +70 C Parameter Input Clock Frequency Output Clock Duty Cycle Short term Cycle to cycle Jitter Short term Period Jitter One-sigma jitter Output Rise Time Output Fall Time Modulation Frequency Symbol Conditions All outputs ICLK=50 MHz, SS OFF ICLK=50 MHz, SS ON SS OFF SS OFF Min. 15 45 Typ. 50 50 80 50 15 0.9 0.9 32 Max. Units 60 55 100 100 100 MHz % ps ps ps ps ns ns kHz tR tF 20% to 80%, CL=15 pF, 50 MHz 80% to 20%, CL=15 pF, 50 MHz ICLK=20 MHz Note1: Cycle-to-cycle jitter is the maximum observed variation between two adjacent cycle's periods over a defined number of observed cycles. The JEDEC specification for the number of cycles observed is 1000 cycles. IDTTM LOW EMI CLOCK GENERATOR 5 IDT5V50017 REV D 040709 IDT5V50017 LOW EMI CLOCK GENERATOR SSCG Thermal Characteristics Parameter Thermal Resistance Junction to Ambient Symbol JA JA JA JC JT Conditions Still air 1 m/s air flow 3 m/s air flow Still air Min. Typ. 150 140 120 40 20 Max. Units C/W C/W C/W C/W C/W Thermal Resistance Junction to Case Thermal Resistance Junction to Top of Case Marking Diagram 8 5 IDT5V50 017DCG #YYWW$ 1 Notes: 4 1. YYWW is the digits of the year and week that the part was assembled. 2. "$" is the assembly mark code. 3. "G" designates RoHS compliant package. 4. "#" is the lot code. 5. Bottom marking: country of origin if not USA. IDTTM LOW EMI CLOCK GENERATOR 6 IDT5V50017 REV D 040709 IDT5V50017 LOW EMI CLOCK GENERATOR SSCG Package Outline and Package Dimensions (8-pin SOIC, 150 Mil. Body) Package dimensions are kept current with JEDEC Publication No. 95 Millimeters Symbol Min Max Inches Min Max 8 E INDEX AREA H 12 D A A1 B C D E e H h L 1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 4.80 5.00 3.80 4.00 1.27 BASIC 5.80 6.20 0.25 0.50 0.40 1.27 0 8 .0532 .0688 .0040 .0098 .013 .020 .0075 .0098 .1890 .1968 .1497 .1574 0.050 BASIC .2284 .2440 .010 .020 .016 .050 0 8 A A1 h x 45 C -Ce B SEATING PLANE L .10 (.004) C Ordering Information Part / Order Number 5V50017DCG 5V50017DCG8 Marking see page 6 Shipping Packaging Tubes Tape and Reel Package 8-pin SOIC 8-pin SOIC Temperature 0 to +70 C 0 to +70 C Parts that are ordered with a "G" after the two-letter package code are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDTTM LOW EMI CLOCK GENERATOR 7 IDT5V50017 REV D 040709 IDT5V50017 LOW EMI CLOCK GENERATOR SSCG Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 For Tech Support www.idt.com/go/clockhelp Corporate Headquarters Integrated Device Technology, Inc. www.idt.com (c) 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA |
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